1. Field of the Invention
The present invention relates to a semiconductor chip or die carrier having a reduced size, and methods for making and using the semiconductor die carrier. In particular, the present invention relates to a semiconductor die carrier affording an external interface having a high-density of electrically conductive contacts concentrated within a very small area.
2. Description of the Related Art
Semiconductor packages typically contain a semiconductor die having bonding pads formed thereon, a plurality of leads connected to the bonding pads of the semiconductor die, and insulative packaging material, such as ceramic or plastic, formed around the semiconductor die and inner portions of the leads. Such a semiconductor package allows the transmission of electrical signals between the semiconductor die and an interface surface, such as a printed circuit board (PCB), via the bonding pads of the semiconductor die, an electrically conductive path between the bonding pads and the leads, the leads themselves, and traces on the interface surface.
In the prior art, various methods are known for providing the electrically conductive path between the semiconductor die and the leads of the semiconductor package. Such methods, commonly referred to as bonding techniques, include C4 (controlled collapse die connection) bonding, wire bonding, and TAB (Tape Automated Bonding).
FIG. 1 is a side view of components of a semiconductor package manufactured in accordance with a conventional C4 bonding technique. With reference to FIG. 1, in C4 bonding, a semiconductor die 101 is selected, and an array of miniature solder balls 102; each for forming a C4 interconnection, is attached to the lower surface of the semiconductor die. The semiconductor die 101 is placed on a multi-layer conductor 103, and then the solder balls are melted to establish permanent C4 interconnections between the die 101 and the multi-layer conductor 103. Leads 105 are attached to the bottom surface of the multi-layer conductor 103 using brazed joints 104 so that electrical signals may be transmitted between the multi-layer conductor and a PCB 106. The PCB 106 includes plated-through-holes (PTHs) 107 within which the leads 105 are mounted and secured, respectively, through use of a solder material 108.
FIG. 2 is a side view of components of a semiconductor package configured in accordance with a conventional wire bonding technique. With reference to FIG. 2, in wire bonding, a semiconductor die 201 having a plurality of bonding pads 202 formed thereon is selected, and one end of a bonding wire 203 is connected to a corresponding bonding pad. The other end of the bonding wire 203 is connected to a package component 204 including insulative material 205 and conductive pads 206 formed thereon. Leads (not shown) extend from the bottom surface of the package component 204 so that electrical signals may be transmitted between the package component and a PCB (not shown).
TAB (Tape Automated Bonding) is similar to the aforementioned wire bonding technique, except that a different type of lead structure is used. More particularly, rather than connecting a semiconductor die to leads such as those discussed above in connection with FIG. 2, the semiconductor die is instead attached to conductive traces printed on a clear plastic substrate.
Conventional semiconductor packages suffer from many deficiencies. Conventional PGA (Pin Grid Array) packages, for example, tend to take up large amounts of circuit board area. For example, at present, the package used for the Intel 486 (trademark) microprocessor, a 168-pin PGA, occupies 1,936 sq. mm of board area. Even greater in area is the Intel PENTIUM (trademark) microprocessor, a 283-pin PGA occupying 2,916 sq. mm of board area. PGA packages generally increase significantly in size as more input/output interconnections are needed, suggesting that future PGA packages for microprocessors will take up even more board area than existing PGA packages.
The manner in which conventional C4 and other bonding technologies are currently being used contributes to the aforementioned area usage problem. In C4 technology, for example, the C4 interconnections provide useful electrical connections, but do not provide an adequate amount of mechanical strength for the types of leads now in use. Moreover, C4 interconnections are not typically applicable for use within pluggable semiconductor packages. Consequently, in PGAs manufactured using conventional C4 bonding technology, the portions of the leads extending externally from the PGA must be spaced apart to a significant extent. Such spacing increases the area of the PCB that will be occupied by the PGA. Moreover, the use of a multi-layer conductor for supporting the semiconductor die within the PGA package also adds to the size and cost of the PGA package. Also, conventional C4 bonding technology can result in problems with individual lead parasitics, inspectability and testing problems, and problems relating to touch-up and repair.
In addition to increasing the size of conventional PGA-type semiconductor packages, the use of leads that are intentionally spread apart to compensate for mechanical insufficiencies and to allow for pluggable and/or non-pluggable mounting, and the use of multi-layer conductors for supporting the semiconductor die within such packages, all contribute to deficiencies associated with conventional PGA-type semiconductor packages. Such deficiencies include a lengthening in the amount of distance that electrical signals must travel within the semiconductor package, which lengthening affects signal propagation times; an increase in the amount of noise imparted to such electrical signals; an elevation in the power requirements for the semiconductor package; and an increase in the complexity of processes required to manufacture the semiconductor package.
Another disadvantage associated with conventional PGA-type semiconductor packages is that such packages, because they frequently are not used with a socket, are commonly mounted on PCBs using conventional PTH technology, thereby necessitating the performance of a soldering step that is not compatible with SMT processing and is not easily reversed. Such PTH mounting can increase the complexity and expense of the manufacturing operation. Also, such PTH mounting is not very suitable for the implementation of repairs in the field. For example, when testing circuit boards for malfunctions and the like in the field, it is often desirable to remove various semiconductor packages to perform tests to see how the board functions in the absence of such packages. PTH mounting often is not suitable for such testing due to the permanence associated with the soldering operation frequently required for PTH mounting. Moreover, solder, because it can make components difficult to replace, can strictly limit upgradability.
The cost of the ceramic packaging material and brazed pin assembly is another disadvantageous characteristic of conventional PGA-type packages. Another disadvantage is that conventional PGA-type packages have low-performance heat sink characteristics. The excessive number of manufacturing processes required to fabricate PGA-type packages is another disadvantage.
From the foregoing, it can be understood that conventional semiconductor packages, such as PGA-type packages, take up large amounts of board space; are frequently not removably pluggable; are not easily tested in the field or during manufacture; and commonly experience greater amounts of noise and have increased power requirements due to the long distances signals must travel within such packages. A most telling characteristic of conventional semiconductor packages is that in all known packages, the space occupied by the entire package is many times greater than the space actually required for the semiconductor die.
As a result of the foregoing limitations, current semiconductor packaging technology is not sufficient to meet the needs of existing and/or future semiconductor and computer technology. Semiconductor packaging technology has already failed to keep pace with semiconductor die technology and, as computer and microprocessor speeds continue to climb, with space efficiency becoming increasingly important, semiconductor packages having even smaller area requirements will be required. The semiconductor packages discussed above fall short of current and contemplated semiconductor packaging requirements.
Accordingly, it is a goal of the present invention to provide a semiconductor die carrier occupying reduced amounts of board area, allowing more contacts to be added to enhance performance and functionality, and capable of meeting the needs of existing and contemplated semiconductor and computer technology.
Another goal of the present invention is to provide a semiconductor die carrier that can be made either compatible with surface-mount technology (SMT) or pluggable to facilitate testing both in the field and during manufacture.
Yet another goal of the present invention is to provide a semiconductor die carrier having signal paths that are reduced in length to reduce noise and decrease necessary power requirements.
A further goal of the present invention is to provide a semiconductor die carrier having a reduced size to allow a reduction in overall size of the system incorporating the die carrier.
Still another goal of the present invention is to provide an SMT-compatible or pluggable semiconductor die carrier which does not use a multi-layer conductor for supporting the semiconductor die so that a very low profile package may be provided.
It is also a goal of the present invention to provide methods for making the using semiconductor die carriers having characteristics such as those discussed above.
These and other goals are achieved by using a semiconductor die carrier comprising an insulative substrate; an array of groups of multiple electrically conductive contacts arranged in rows and columns on the insulative substrate, wherein the groups from adjacent rows are staggered as are the groups from adjacent columns, and a portion of each group overlaps into an adjacent row or an adjacent column of the groups of the array; a semiconductor die; and means for providing electrical connection between the semiconductor die and the conductive contacts.
Also, a method of manufacturing a semiconductor die carrier may be used, the method comprising the steps of forming an insulative substrate; arranging an array of groups of multiple electrically conductive contacts in rows and columns on the insulative substrate, such that the groups from adjacent rows are staggered as are the groups from adjacent columns, and a portion of each group overlaps into an adjacent row or an adjacent column of the groups of the array; providing a semiconductor die; and electrically connecting the semiconductor die and the conductive contacts.
The aforementioned goals and other goals are also achieved by using a semiconductor die carrier comprising an insulative substrate; a plurality of leads each having an external portion extending out of the semiconductor die carrier from a lower surface of the insulative substrate and an internal portion located within the semiconductor die carrier at an upper surface of the insulative substrate; a semiconductor die positioned above the insulative substrate; and a layer of conductive material in contact with conductive portions of the semiconductor die and also in contact with the internal portions of the leads.
Also, a method of manufacturing a semiconductor die carrier may be used, the method comprising the steps of fabricating or manufacturing an insulative substrate; providing a plurality of leads each having an external portion extending out of the semiconductor die carrier from a lower surface of the insulative substrate and an internal portion located within the semiconductor die carrier at an upper surface of the insulative substrate; positioning a semiconductor die above the insulative substrate; and electrically connecting conductive portions of the semiconductor die and the internal portion of the leads using a layer of conductive material in contact with conductive portions of the semiconductor dies and also in contact with the internal portions of the leads.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory, and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present invention and, together with the general description, serve to explain the principles of the present invention.